1. Field of the Invention
The invention relates to telecommunication field, and more particularly to apparatus and method for demultiplexing a frequency division multiplexed signal using a polyphase digital filter network.
2. Description of Prior Art
The use of satellites with multiple spot beam is a major step in increasing the capabilities of satellite communication. Multiple beam satellites have the advantage of having high gain and allowing the reuse of the same frequency band in geographically separated beams. The use of multiple spot beams requires additional switching on-board the satellite. This switching can be done either in the RF, IF or the baseband. Switching at the RF and IF necessitates the use of Time Division Multiple Access (TDMA) in the uplink which could lead to high rate modems in the earth stations, therefore increasing the cost of earth stations. On-board switching in the baseband requires down-conversion, demultiplexing and demodulation of the uplink data prior to switching and remultiplexing, remodulation and upconversion after switching to form the downlink. The part of the signal processing in the baseband is called On-board Baseband Processing (OBP). The use of the OBP results in a considerable flexibility in the choice of the access scheme and either TDMA or Frequency Division Multiple Access (FDMA) can be used. For the payloads with OBP, the use of FDMA is considered on the uplink to reduce ground station cost. On the other hand, Time Division Multiplexing (TDM) is used for its power efficiency on the downlink.
Moreover, use of FDMA on the uplink reduces the size of the earth terminal as compared to TDMA. However, the price paid is the increased complexity of the spacecraft payload. While a single demodulator is sufficient for demodulation of high bit rate TDMA on the uplink, several demodulators are required for the demodulation of the FDMA carriers received by the satellite. A solution to this problem is the use of a multi-carrier demodulator, referred to as a group demultiplexer/demodulator. Group demultiplexing is needed, for example, in the digital signal processing payloads if the uplink uses FDMA or some other type of spectrum sharing such as MF-TDMA or MF-CDMA. The more important and computational intensive section, referred to as the group demultiplexer, divides the incoming composite spectrum into separate channels. The second section, the demodulator, recovers the digital data for each individual channel.
There are several techniques for the group demultiplexer design. A straightforward method is per-channel filtering. In this method, a separate filter is used for each channel. This is only feasible for a small number of channels. For a large number of channel, sharp filters with many taps are required. Another method is the FFT/IFFT or frequency-domain filtering. In this method, a Fast Fourier Transform (FFT) is used to find the frequency spectrum of the composite FDM signal. Following the FFT, the frequency-domain coefficients are multiplied by coefficients of a filter in order to determine the frequency-domain samples falling into each of the carrier channels. For each set of frequency-domain coefficients, an Inverse FFT (IFFT) is used to recover the time-domain samples of the modulated carriers. This method is much less complex than the per-channel approach, while having a great degree of flexibility.
Another method for the implementation of the group demultiplexer is the polyphase/FFT method. In this method, a digital filter bank is implemented in cascade with an DFT processor, and preferably a FFT processor to provide better efficiency. This technique can be used when the bandwidths of the channels are equal and fixed. FIG. 1 is a block diagram of a polyphase/FFT group demultiplexer according to the prior art and generally designated at 10. Input Y(z) at 12, 12xe2x80x2 and outputs Xk(zN) at 14, 14xe2x80x2 with k=0, . . . , Nxe2x88x921, are in complex sampled form, as well known in the art, with solid lines 12, 14 representing the In-phase (or I) and dotted lines 14, 14xe2x80x2 representing the Quadrature-phase (or Q) components of different signals. The notation used for the representation of the signals and delay elements is in the Z-domain. The elements specified by Zxe2x88x92k in FIG. 1 represent a delay of rT, normally implemented using shift registers of length r. That is, if the input to Zxe2x88x92k is a sample of a time signal u(t) at time kT, denoted by u[n], its output will be a sample of the signal u(t) at time nTxe2x88x92kT, denoted by u[nxe2x88x92k], where T is the time duration between two consecutive samples. The symbol Y(z) represents the Z-transform of a composite signal y[n] consisting of N frequency multiplexed signals represented as follows:                               Y          ⁡                      (            z            )                          =                              ∑                          n              =                              -                ∞                                                    +              ∞                                ⁢                                    y              ⁡                              [                n                ]                                      ⁢                          z                              -                n                                                                        (        1        )            
The outputs Xi(zN), i=0,1, . . . , Nxe2x88x921 represent the N individual signals after demultiplexing. The Z-transform being represented as a function of ZN rather than z represents a decimation of the outputs by N, i.e., only every Nth sample of xi[n] is retained. This is consistent with the Nyquist sampling theorem, relating the number of samples required for discrete representation of a signal to its bandwidth. That is, since the bandwidth of each of the N individual channels is 1/Nth of the total bandwidth occupied by the composite signal y(t), to represent each of these individual signals, we need only to have 1/Nth of the samples required for perfect reconstruction of y(t).
The digital filter network 15 comprises a filter bank 16 shown in FIG. 1 consisting of sub-filters Hi(zN), i=0,1, . . . , Nxe2x88x921, designated at 17, which is derived from a single prototype Finite Impulse Response (FIR) filter, H(z), through a decimation by N. That is, each sub-filter Hi(ZN) consists of 1/Nth of the coefficients of H(z). Denoting the coefficients of the prototype filter by hi, i=0,1, . . . , NLxe2x88x921, the coefficients of the sub-filter, H0(zN), are h0, hN, h2N, . . . , hN(Lxe2x88x921), and the coefficients of the sub-filter, H1(zN), are h1, hN+1, h2N+1, . . . , hN(Lxe2x88x921)+1. In general, the coefficients of the ith sub-filter, Hi(zN), are hi, hN+i, h2N+i, . . . , hN(Lxe2x88x921)+i. The derivation of the sub-filters from the prototype filter is based on the following factorization:                               H          ⁡                      (            z            )                          =                                            ∑                              n                =                0                                            NL                -                1                                      ⁢                                          h                n                            ⁢                              z                                  -                  n                                                              =                                                    ∑                                  i                  =                  0                                                  N                  -                  1                                            ⁢                                                z                                      -                    i                                                  ⁢                                                      ∑                                          k                      =                      0                                                              L                      -                      1                                                        ⁢                                                            h                                              kN                        +                        i                                                              ⁢                                          z                                              -                        kN                                                                                                                  =                                          ∑                                  i                  =                  0                                                  N                  -                  1                                            ⁢                                                z                                      -                    i                                                  ⁢                                                                            H                      i                                        ⁡                                          (                                              z                        N                                            )                                                        .                                                                                        (        2        )            
The switches 18, 18xe2x80x2 at the input of the sub-filters 17 close every N samples connecting the outputs of the shift registers 20 to different sub-filters. That is, each sub-filter operates at a rate which is 1/Nth that of the sample rate of the input signal, y[n]. Multiplication of output signals Ai(n) by wi, i=0,1, . . . , Nxe2x88x921 generated at outputs 19, 19xe2x80x2, where w=exe2x88x92ixcfx80/N is performed by a set of N multipliers 22 and results in a phase shift of ixcfx80/N to produce filtered output signals A*i(n) at outputs 21, 21xe2x80x2, from which the FFT processor 23 finds the Discrete Fourier Transform (DFT) as defined by:                               B          k                =                              ∑                          i              =              0                                      N              -              1                                ⁢                                    A              i                        ⁢                          ⅇ                              j                ⁢                                                      2                    ⁢                    π                                    N                                ⁢                ik                                                                        (        3        )            
Finally, the alternate samples of each of the N outputs 25, 25xe2x80x2 of the FFT processor are inverted by the multipliers 24 to produce demultiplexed output signals Xk(ZN) at outputs 14, 14xe2x80x2.
From the foregoing, it can be seen that the number of multipliers required for the implementation of the polyphase filter network is NL, which correspond to coefficients h0, h1, h2, . . . , hNLxe2x88x921 of the prototype filter. Such a number of multipliers may represents a limiting factor in the context of payload optimization especially where a high number of channels is to be handled by a satellite On-board demultiplexer.
It is therefore an object of the present invention to provide apparatus and method for demultiplexing a frequency division multiplexed input signal which involves a reduced number of multipliers or multiplying steps.
According to the above object, from a broad aspect of the present invention, there is provided a polyphase digital filter network based on a linear phase prototype filter for use in a group demultiplexer for generating N output data signals associated with N channels from a corresponding Frequency Division Multiplexed input signal Y(n), said linear phase prototype filter comprising N sub-filters being characterized by L coefficients forming NL coefficients for said prototype filter. The polyphase digital filter network comprises Lxe2x88x921 Zxe2x88x92N shift registers in series receiving the multiplexed input signal Y(n) to produce Lxe2x88x921 corresponding shifted signals Y(nxe2x88x92rN), with r=1, . . . , Lxe2x88x921, and a set of p first adder sections each receiving a distinct pair of signals from the multiplexed input signal Y(n) and the shifted signals Y(nxe2x88x92rN). The filter network further comprises a set of q multiplier sections including p first multiplier sections each being coupled to a respective output of a corresponding one of the first adder sections for combining each said output with a corresponding set of N transformed filter coefficients gi derived from the coefficients of the linear phase prototype filter, the set of q multiplier sections including a further multiplier section receiving shifted signal   Y  ⁡      (          n      -                        (                                    L              -              1                        2                    )                ⁢        N              )  
where L is odd for combining thereof in parallel with a corresponding set of s further transformed filter coefficients gi derived from the coefficients of the linear phase prototype filter. The filter network further comprises a set of N second adder sections each being coupled to distinct outputs of the multiplier sections for producing a corresponding set of N transformed signals Ck(n), with k=0, . . . , Nxe2x88x921; and a set of t third adders each receiving a distinct pair of signals {CT(n),CTxe2x80x2(n)} from the transformed signals Ck(n) for producing a first filtered signal A0(n) and a set of Nxe2x88x921 filtered signals Ak(n+k), with k=1, . . . , Nxe2x88x921.
According to a further broad aspect of the present invention, there is provided a polyphase/DFT digital group demultiplexer for generating N output data signals associated with N channels from a corresponding Frequency Division Multiplexed input signal Y(n), comprising a polyphase digital filter network based on a linear phase prototype filter formed by N sub-filters being characterized by L coefficients forming NL coefficients for said prototype filter. The polyphase digital filter network comprises Lxe2x88x921 Zxe2x88x92N shift registers in series receiving the multiplexed input signal Y(n) to produce Lxe2x88x921 corresponding shifted signals Y(nxe2x88x92rN), with r=1, . . . , Lxe2x88x921; and a set of p first adder sections each receiving a distinct pair of signals from the multiplexed input signal Y(n) and the shifted signals Y(nxe2x88x92rN). The filter network further comprises a set of q multiplier sections including p first multiplier sections each being coupled to a respective output of a corresponding one of the first adder sections for combining each said output with a corresponding set of N transformed filter coefficients gi derived from the coefficients of the linear phase prototype filter, the set of q multiplier sections including a further multiplier section receiving shifted signal   Y  ⁡      (          n      -                        (                                    L              -              1                        2                    )                ⁢        N              )  
where L is odd for combining thereof with a corresponding set of s further transformed filter coefficients gi derived from the coefficients of said linear phase prototype filter. The filter network further comprises a set of N second adder sections each being coupled to selected outputs of the multiplier sections for producing a corresponding set of N transformed signals Ck, with k=0, . . . , Nxe2x88x921; and a set of t third adders each receiving a distinct pair of signals {CT(n),CTxe2x80x2(n)} from the transformed signals Ck(n) for producing a first filtered signal A0(n) and a set of Nxe2x88x921 filtered signals Ak(n+k), with k=1, . . . , Nxe2x88x921. The filter network further comprises a set of Nxe2x88x921 shift registers Zxe2x88x92k receiving said. filtered signals Ak(n+k) to produce Nxe2x88x921 corresponding filtered signals Ak(n), with k=1, . . . , Nxe2x88x921. The group demultiplexer further comprises a set of N phase offset multipliers receiving the filtered signals A0(n) and Ak(n) forming a set of filtered signals Ak(n), with k=0, . . . , Nxe2x88x921, for combining thereof with a corresponding set of N phase offset parameter wk, with k=0, . . . , Nxe2x88x921, to produce a corresponding set of phase offset filtered signals A*k(n); Discrete Fourier Transform processor means for generating a set of N processed output signals Bk(n) from said corresponding set of phase offset filtered signals A*k(n), with k=0, . . . , Nxe2x88x921; and a set of N output alternate inverting multipliers each receiving a corresponding one of the set of processed output signals Bk(n) to generate the N output data signals associated with the N channels.
According to a still further broad aspect of the present invention, there is provided a method of demultiplexing a Frequency Division Multiplexed input signal Y(n) for generating N output data signals associated with N channels, the method comprising the steps of: i) generating Lxe2x88x921 shifted signals Y(nxe2x88x92rN), with r=1, (lxe2x88x921)N, from the multiplexed input signal Y(n); ii) coupling p pairs of distinct signals from the multiplexed input signal Y(n) and the shifted signals Y(nxe2x88x92rN) to produce p corresponding pairs of coupled output signals; iii) combining each said pair of output signals with a corresponding set of N transformed filter coefficients derived from coefficients of a linear phase prototype filter; iv) combining shifted signal   Y  ⁡      (          n      -                        (                                    L              -              1                        2                    )                ⁢        N              )  
with a corresponding set of s further transformed filter coefficients derived from the coefficients of the linear phase prototype filter, whenever L is odd; v) coupling the results of the combining steps to produce N transformed signals Ck, with k=0, . . . , Nxe2x88x921; vi) coupling distinct pair of signals {CT(n),CTxe2x80x2(n)} from the transformed signals Ck(n) for producing a first filtered signal A0(n) and a set of Nxe2x88x921 filtered signals Ak(n+k), with k=1, . . . , Nxe2x88x921; vii) shifting the filtered signals Ak(n+k) to produce Nxe2x88x921 corresponding filtered signals Ak(n), with k=1, . . . , N-xe2x88x921; viii) phase offsetting the filtered signals A0(n) and Ak(n) forming a set of filtered signals Ak(n), to produce a corresponding set of phase offset filtered signals A*k(n); ix) applying a Discrete Fourier Transform on the phase offset filtered signals A*k(n) to generate a set of N output signals Bk(n), with k=0, . . . , Nxe2x88x921; and x) alternately inverting the output signals Bk(n) to generate the N output data signals associated with the N channels.